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CorePCIF v4.0
Utilization Statistics
Utilization Statistics
Table 2 and Table 3 on page 8 give the CorePCIF device utilization for both 32-bit and 64-bit implementations. The
numbers in these tables are typical and will vary based on the actual core configuration and the synthesis tools used.
CorePCIF device utilization and performance varies, depending on which features are implemented. The core has
approximately 50 configuration parameters. Table 2 (32-bit) and Table 3 on page 8 (64-bit) give example utilizations for
typical implementations. The exact parameter settings are detailed in Table 4-4 on page 39 .
Table 2 · 32-Bit CorePCIF Device Utilization
Implementation
Family
Cells or Tiles
Combinatorial Sequential
Total
Memory Blocks
Device
Utilization
SMALL32
544
177
721
0
AFS600
5%
TARG32
MAST32
TARGDMA32
TARGMAST32
SMALL32
TARG32
MAST32
TARGDMA32
TARGMAST32
SMALL32
TARG32
MAST32
TARGDMA32
TARGMAST32
SMALL32
TARG32
MAST32
TARGDMA32
TARGMAST32
SMALL32
TARG32
MAST32
TARGDMA32
TARGMAST32
SMALL32
TARG32
MAST32
TARGDMA32
TARGMAST32
Fusion?
IGLOO?/e
ProASIC?3/E
ProASIC3L
SmartFusion2
ProASIC PLUS ?
RTAX-S
Axcelerator?
RTSX-S
661
1,434
1,594
2,698
405
555
975
977
1576
658
716
1,479
1,644
3,020
350
465
799
867
2,562
381
453
830
874
1,677
387
491
1,134
966
1,359
203
383
369
658
275
359
519
523
797
215
208
422
377
697
178
244
422
414
2,206
180
210
393
380
653
221
282
507
465
834
864
1,817
1,963
3,356
680
914
1494
1500
2373
873
924
1,901
2,021
3,717
528
709
1,221
1,281
4,768
561
663
1,223
1,254
2,330
608
773
1,641
1,431
2,193
2
2
2
2
0
1
1
1
1
0
4
4
4
4
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
AGLE600
AGL600
A3PE600
A3P600
M2S050T
M2S050T
M2S050T
M2S050T
M2S050T
APA150
APA150
APA150
APA300
APA300
RTAX250S
RTAX250S
RTAX250S
RTAX250S
RTAX1000S
AX500
AX500
AX500
AX500
AX500
RT54SX32S
RT54SX32S
RT54SX32S
RT54SX72S
RT54SX72S
6%
13%
14%
24%
1%
2%
3%
2%
4%
14%
15%
31%
25%
45%
12%
17%
29%
30%
26%
7%
8%
15%
16%
29%
21%
27%
57%
24%
36%
v4.0
7
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